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Instruction and data cache optimizations

R&D task number: G4RD4

Study Geant4 performance and investigate methods to reduce bottlenecks due to issues related to memory latency and bandwidth

Performance analysis of realistic Geant4 simulations have shown that memory related issues such as instruction cache misses and TLB (translation lookaside buffer) cache misses are the most significant factors currently limiting Geant4 performance.

This task will investigate potential ways for overcoming these bottlenecks, by creating prototype with different degree of revision or structural changes to Geant4. These could include refinements or revisions to specific components and the investigation of major structural revisions, such as the prototype of "stateless tracking" in the separate R&D task.

Lead and main developers

  • Guilherme Amadio​
  • John Apostolakis

Effort estimate

This is expected to be a continuous task to monitor Geant4 performance and propose code changes based on monitoring results.

Pointers to information

Report on Geant4 performance: https://indico.cern.ch/event/809405/

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